Effective Partitioning of Static Global Buses for Small Processor Arrays

This paper shows an effective partitioning of static global row/column buses for tightly coupled 2D mesh-connected small processor arrays (“mesh”, for short). With additional O(n/m (n/m + log m)) time slowdown, it enables the mesh of size m×m with static row/column buses to simulate the mesh of the larger size n×n with reconfigurable row/column buses (m ≤ n). This means that if a problem can be solved in O(T) time by the mesh of size n×n with reconfigurable buses, then the same problem can be solved in O(T n/m (n/m + log m)) time on the mesh of a smaller size m×m without a reconfigurable function. This time-cost is optimal when the relation n ≥ m log m holds (e.g., m = n for ε > 0). Keywords—Processor Array, Dynamically Reconfigurable Bus, Statically Partitioned Bus, Scaling-Simulation, Polylogarithmic Time Simulation